Technical Field
The disclosure is related to the thin film transistor field, and more particular to a low temperature poly-silicon thin film transistor and a method for manufacturing a low temperature poly-silicon thin film transistor.
Related Art
Refer to FIG. 1. FIG. 1 is the schematic structure of the low temperature poly-silicon thin Film transistor of the prior art.
As shown in FIG. 1, the Low temperature poly-silicon thin Film transistor of the prior art comprises sequentially a substrate, a SiNx layer, a SiOx substrate layer an a-Si layer, a doped region doped with different doses of P31 (phosphorus having relative molecular mass of 31), a GE layer (gate metal layer), a source (source metal) layer, and a drain (drain metal) layer. The source metal layer and the drain metal layer are correspondingly formed in the depression region channel as indicated by the ILD Via Hole arrow shown in FIG. 1 and connect with the doped region.
It can be seen from FIG. 1 that the vertical hole configuration for the depression region has greater affection on the source metal layer and the drain metal layer. For example, with increase of the film thickness of the ILD (interlayer dielectric layer), the line width of the source metal layer and the drain metal layer become narrow. The troubles in the process gradually emerge. In particular, for the super-resolution LTPS and the final products, the line may possibly break for the source metal layer and the drain metal layer formed in the depression region channel ILD via Hole, such as contact with the edges and corners of the depression region channel ILD via Hole. Secondly, the source metal layer and the drain metal layer may not completely fill the depression region channel ILD via Hole such that small gaps are formed. Thus it is easy to decrease the reliability of the product. The yield rate and the pass rate cannot be guaranteed either.